1. Field of the Invention
This invention relates to a read-out/write-in circuit for a semiconductor memory device.
2. Description of the Related Art
In recent years, electrically erasable and programmable nonvolatile memories or EEPROMs (Electrically Erasable Programmable Read Only Memories) are widely used in electronic devices such as mobile phones and digital still cameras. The EEPROM is provided with a memory cell having a floating gate and a control gate. It stores binary data or more than two-level data with electric charges stored in the floating gate, and the stored data is read out by sensing a difference in conductance between a source region and a drain region, which depends on the electric charges stored in the floating gate.
Memory cells in the EEPROM are classified into two types that are a stacked-gate type which has stacked layers of the floating gate and the control gate on a semiconductor substrate and a split-gate type in which both the floating gate and the control gate face a channel in a semiconductor substrate.
The control gate is connected to a word line in the split-gate type memory cell. When erasing the data, a high voltage is selectively applied to a word line selected by a decoder circuit. As a result, the data in the memory cell is erased by extracting the electric charges stored in the floating gate to the control gate. That is, when erasing the data in the memory cell, the high voltage is applied to the selected word line while a ground voltage is applied to non-selected word lines.
This kind of EEPROM is disclosed in U.S. Pat. Nos. 5,029,130, 5,045,488 and 5,067,108 and Japanese Patent Application Publication Nos. H11-274329, 2005-159336 and 2000-173278, for example.
However, forming EEPROM circuit as described above requires high withstand voltage transistors that tolerate the high voltage applied when erasing the data. If a large number of high voltage transistors are required, it causes a problem that a die size of the EEPROM becomes too big.